Voltage and temperature compensating source

ABSTRACT

A positive temperature coefficient generator for offsetting negative temperature coefficients normally associated with integrated circuits PN junctions which includes a pair of interconnected circuits. Each circuit includes at least a pair of PN junctions for developing a resultant positive temperature coefficient output signal which is independent of the current levels existing at the circuit PN junctions and which is related only to the ratio of the areas defining the PN circuit junctions.

United States Patent [1 1 Marley et al.

[451 Sept. 23, 1975 VOLTAGE AND TEMPERATURE COMPENSATING SOURCE inventors: Robert R. Marley, Phoenix; Walter C. Seelhach, Scottsdale, both of Ariz.

Assignee: Motorola, Inc., Chicago, Ill

Filed: Mar. 1, 1974 Appl. No.: 447,198

U.S. Cl. 323/19; 323/l; 323/68 Int. Cl. i. GOSF 3/08 Field of Search 7. 307/296, 297, 299 A;

323/1, 4, l6, I9, 22 T, 68

References Cited UNITED STATES PATENTS 2/l974 Bernacchi 307/297 Keller et al H 323/22 T Horichi 323/22 T Primary ExaminerA. D. Pellinen Attorney, Agent. or FirmVincent J. Rauner; Kenneth R. Stevens [57] ABSTRACT A positive temperature coefficient generator for offsetting negative temperature coefficients normally associated with integrated circuits PN junctions which includes a pair of interconnected circuits. Each circuit includes at least a pair of PN junctions for developing a resultant positive temperature coefficient output signal which is independent of the current levels existing at the circuit PN junctions and which is related only to the ratio of the areas defining the PN circuit junctions.

7 Claims, 4 Drawing Figures VOLTAGE AND TEMPERATURE COMPENSATING SOURCE BACKGROUND OF THE INVENTION 1. Field of the Invention This invention relates to a regulator circuit, and more particularly to a regulator circuit for integrated circuits which have selectable temperature dependency and are voltage independent.

2. Discussion of the Prior Art Uncompensated integrated bipolar devices possess a negative temperature coefficient due to their base-toemitter junction applied voltages. For silicon transistors negative temperature coefficient typically can vary anywhere from I .5mv/C to 2.0mv/C.

One prior art solution for avoiding the undesired temperature coefficients generally is illustrated by the following formula:

AV (KI I (+K2).

The Kl portion of the equation could represent the negative temperature coefficient term inherent in bipolar transistors, as described above. In order to offset the negative temperature coefficient term Kl, a zener diode is sometimes included in the overall circuit as represented by the positive term K2. As the zener diode possesses a positive temperature coefficient, the overall temperature coefficient of the circuit can be theoretically adjusted to approximately zero. The combination of the K1 and K2 terms would be equal to zero and thus the overall temperature coefficient would be zero. Therefore, circuits can be designed which are independent of both temperature and supply voltage variations.

Unfortunately implementation of this form of compensation with a zener diode in integrated circuit form results in two primary disadvantages. Firstly, a zener diode operates on relatively high voltages and this does not particularly lend itself to high density integrated circuits due to power dissipation considerations. Secondly. from a fabrication standpoint zener diodes do not lend themselves to high yield, high reproducibility, and economical implementation in high density bipolar integrated circuit technology.

Another more recent approach is illustrated by the equation AV NV I m1) AT AT AT Again the All s] A'I' term represents a negative temperature coefficient inherent in bipolar transistors. The A(A\/ ;)/AT term corresponds to a positive temperature coefficient voltage which is generated by employing the characteristics of PN junctions in integrated circuit form. Thus the circuit representation of these two terms can be combined in an additive and adjustable manner in order to yield a net positive. net negative or substantially zero temperature coefficient compensation for the overall circuit.

Nonetheless, this last mentioned approach as implemented in prior art suffers major drawbacks because in its circuit implementation the AV term is current level dependent. That is. the absolute value of the AV term is established by a ratio of currents within the circuit. Furthermore. the magnitude of the output voltage capable of being generated is approximately represented by KAV,,,.;, where K is a resistor ratio within the circuit.

Thus, in order to increase the magnitude of the actual generated output voltage, it is necessary either to increase the current density ratio with its obvious attendant disadvantages, or to increase the K factor which has a practical limitation when implemented in integrated circuit form. More specifically, integrated circuit processing techniques do not permit large AV -s because of dual limits of bulk device properties at high current densities and the larger dependence upon leakage current at the lower current densities.

SUMMARY OF THE INVENTION It is therefore an object of the present invention to provide an improved positive temperature coefficient generating circuit which can be readily combined in integrated circuit form with a wide variety of bipolar and diode generating circuits for obtaining highly regulated output signals which have adjustable temperature dependency and are voltage independent.

Another object of the present invention is to provide a temperature and voltage fully compensated generating circuit which is capable of generating increased output voltages with attendant minimization of circuit current density ratio, and with optimization of resistor diminsioning so as to be more advantageously implementable in high density integrated circuit form.

Another object of the present invention is to provide an improved positive temperature coefficient generating circuit which is current independent and thus more highly regulated than prior art current dependent generators.

A further object of the present invention is to provide an improved positive temperature coefficient generating circuit wherein its generated output signal is readily adjustable relative to device junction dimensions independent of current levels and processing variations.

In accordance with the aforementioned objects the present invention provides a positive temperature coefficient generator for offsetting negative temperature coefficients normally associated with integrated circuits PN junctions which includes a pair of interconnected circuits. Each circuit includes at least a pair of PN junctions for developing a resultant positive temperature coefficient output signal which is independent of the current densities existing at the circuit PN junctions and which is related only to the area defining the PN circuit junctions.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a schematic diagram illustrating the positive temperature coefficient voltage generating circuit of the present invention.

FIG. 2 is a schematic diagram illustrating the incorporation of the positive temperature coefficient voltage generating circuit, as essentially shown in FIG. 1, combined with an additional non-compensated voltage gencrating circuit for providing an overall voltage and temperature compensated source having particular applicability as a biased driver or voltage source for medium and large scale internal logic elements.

FIG. 3 is a schematic diagram illustrating the incorporation of the positive temperature coefficient voltage generating circuit, as essentially shown in FIG. 1, with additional voltage generating circuitry for providing a biased driver or voltage source which is fully compensated for supply voltage variations and which possesses variable temperature adjustment characteristics so as to provide driving capability for either internal or external medium or large scale integrated circuit devices.

FIG. 4 is a schematic diagram in partial cross-section generally illustrating the implementation of the circuit of the present invention in integrated circuit form.

DESCRIPTION OF THE PREFERRED EMBODIMENTS Now referring to FIG. 1, it illustrates the basic positive temperature coefficient voltage generating circuit of the present invention. The basic circuit includes input terminal means for receiving a negative supply voltage V In the preferred embodiment, this value is approximately 5.2 volts, but an operational range of -2.0 volts to 10.0 volts is also suitable for certain applications. A resistor 11 is connected between another source of potential (ground), and node 12. Also connected to node 12 is the collector terminal of a multiemitter NPN transistor 13, a resistor 14, and the base terminal of NPN transistor 15. A node 16 is also established between the collector terminal of transistor 15, the base terminal of transistor 13, and the other end of resistor 14. Interconnection line 17 connects the plu rality of emitter terminals of transistor 13 to the base terminal of multi-emitter NPN transistor 18 and also to the collector terminal of transistor 19. The emitter terminal of transistor is connected to the collector terminal of transistor 18 at node 20, and a resistor 21 is connected between node and the base terminal of transistor 19. The plurality of emitter terminals of transistor 18 are connected by means of line 22 to terminal 10.

It can be shown that if resistor 21 is selected to have a value equal to twice the value of resistor 14, the circuit is further compensated from a process standpoint as resistor 21 compensates for possible beta variations due to negligible effect of base current flow into transistors l3 and 19.

The circuit of FIG. 1 is implemented in integrated circuit form as schematically illustrated in FIG. 4 in accordance with well known bipolar semiconductor processing techniques. Conventional diffusion, photolithography, isolation, and interconnection steps are employed to form the circuit generally illustrated at 23 on a semiconductor substrate 24. In the preferred embodiment devices are shown as NPN bipolar transistors, but the invention is equally applicable to PNP transistors as well.

OPERATION OF FIG. 1

The circuit of FIG. 1 is implemented in integrated circuit form by employing bipolar transistors possessing high beta characteristics. Typically, beta is greater than I00 for achieving optimum results. With the beta characteristics greater than I00, base current i is much less than the collector current for the individual transis- It 'I' (ll In I "It Equation l sets forth the basic Ebers-Moll model where:

k is Boltzmanns constant;

T is absolute temperature;

q is the charge of an electron;

I is the current level; and

a represents a constant associated with the particular integrated circuit process being used and the PN junction area.

The voltage generated across resistor 14 is given by: VR ar-( HE( BE( m:( )I This equation in rearranged form is derived in a well known manner by applying Kirchoffs law to the loop comprising the transistors 13, 15, 18 and 19, as indi cated in parentheses. Since the effects of base current into transistors 13 and 19 can be eliminated. current 11 flowing through transistor 13 also flows through transistor 19, and similarly current 12 flowing through transistor 15 also flows through transistor 18. Accordingly, substituting equation 1 for each of its associated devices into equation 2 yields the following:

3 k T II It VR q In T In k T I: I 12 q In a n "w dimension identical to the emitter area forming transistor 19, then M S. This relationship also holds true for the path constituted by transistors 15 and 18 having 12 flowing therethrough. In this instance, N is employed to designate the ratio of the emitter areas of multi-emitter transistor 18 over the area of transistor 15. Thus for equation 3, it can be seen that the base-to-emitter voltage equation for transistors 13 and 18 contain an M and an N factor, respectively.

Rearranging equation 3 yields:

(4) VR= ln(MXN].

An examination of equation 4 shows that the positive temperature coefficient voltage generated across resis tor I4 is solely dependent upon the product of the areas of multi-emitter transistors 13 and I8, as the factor (k T/q) is a constant for given transistor fabricated in integrated circuit form. Not only does the circuit of FIG. 1 provide a positive temperature coefficient voltage generating source, but also the magnitude can be readily adjusted solely on the basis of the respective emitter areas of transistors 13 and 18, as represented by M and N, respectively. A further inspection of equation 4 also reveals that the absolute value of VR is independent of the currents flowing in the circuit. Moreover, the actual value of VR can be readily adjusted upwardly or downwardly independent of circuit resistor ratio, simply by varying the product of M X N. Finally, the process term a is also absent from the final equation and thus VR is also process independent.

Now referring to FIG. 2, it illustrates an implementa tion incorporating the circuit of FIG. 1 with the other circuit elements in order to provide overall temperature and voltage compensated sources. With minor modification circuit block constitutes the positive temperature coefficient voltage circuit of FIG. 1 for generating a positive temperature coefficient voltage VR across resistor 26. An amplifying circuit 27 is connected to the generating circuit 25 to provide a temperature and voltage compensated output voltage V and a current source drive voltage V1 capable of driving a plurality of current sources as depicted at 29.

Now referring to the specific details ofgcnerating circuit 25, it is seen that a multi-emitter transistor 30 is connected by means of line 31 to the collector terminal of transistor 32. In a manner identical to that previously described with reference to FIG. 1, transistors 30 and 32 function and operate in an identical manner to transistors 13 and 19, respectively. Likewise transistor 33, multi-emitter transistor 34, and resistor 35 correspond to transistors l5, 18 of FIG. 1 and resistor 21, respectively, and as described these elements function to gen erate a positive temperature coefficient voltage across resistor 26.

Also included within circuit 25 is a negative temperature coefficient voltage generating source indicated generally at 36. Circuit 36 comprises a transistor 37 connected at its collector terminal to resistor 26, and at its emitter terminal to the negative supply V,;,; at terminal 38 by means of transistor 39. The base terminal of transistor 37 is connected to a node 40 and to the base terminal of transistor 33. Connected across the base emitter terminals of transistor 37 is a resistor 41. The circuit 36 generates a negative temperature coefficient voltage which is applied by line 42 to node 40.

Accordingly, node 40 provides a net voltage (V,.;,.;) compensated and selectable temperature compensated to the amplifier circuit means 27 by means of line 43.

The amplifier circuit means 27 comprises a pair of transistors 44, 45, and suitable load resistors 46 and 47 in order to generate a final compensated voltage V,,,,, at output terminal 28.

Transistor 39 is a current level setting device which establishes a predetermined value of current conduction therethrough, and since the base terminal of transistor 39 is connected to the collector terminal of transistor 32 the current through transistor 32, corresponding to current ll as described with reference to FIG. 1, is controlled precisely.

In this embodiment, the regulated and compensated current generated by circuit 25 is also employed to drive current sources generally depicted at 29, which by way of example may include a plurality of transistors.

Now referring to FIG. 3. it illustrates another embodiment incorporating the basic circuit of FIG. I for providing a voltage and temperature compensated source which is capable of driving internal and external logic circuits. Again in a similar manner to that described with reference to FIGS. 1 and 2, the overall circuit comprises a positive temperature coefficient voltage generating section generally shown at 48 and an amplifying section responsive thereto and depicted at 50.

Transistors 52 and 54 correspond to transistors 13 and 19, and transistors 56 and 58 correspond to transistors l5 and 18, respectively, and function to generate a positive temperature coefficient voltage VR across resistor 60, as explained above with respect to FIG. 1. In this version, a resistor 62 is connected across the base-to-emitter terminals of transistor 56 for generating the negative temperature coefficient voltage which is summed with the positive temperature coefficient voltage VR at node 66. This signal is then amplified by circuit 50 to provide a compensated output voltage at a pair of terminals and 72, respectively. The resul' tant voltage at node 66 is developed across resistors 74 and 76 in order to provide an output signal at terminal 72 by means of biasing resistor 78, transistor 80, diode 82, and finally output transistor 84. Similarly, the voltage generated at the lower end of resistor 76 is applied by means of transistor 86 to output terminal 70. Finally, a stabilizing capacitor 88 is connected between the base terminal of transistor 84 and the collector of transistor 58, and resistor 90 and diode 92 provide biasing for the output circuits contained in the amplifier section 50.

While the invention has been particularly shown and described in reference to the preferred embodiments thereof, it will be understood by those skilled in the art that changes in form and details may be made therein without departing from the spirit and scope of the invention.

What is claimed is:

1. An integrated circuit voltage and temperature compensated circuit comprising:

a. a reference impedance coupled to a voltage source, said voltage source generating a first and second current;

b. a first path coupled to said impedance means for receiving said first current;

c. a second path coupled to said reference impedance for receiving said second current;

d. said first current path including at least two serially interconnected PN junctions for generating a first differential voltage;

e. said second current path including at least two serially interconnected PN junctions for generating a second differential voltage; and

f. said reference impedance means being responsive to said first and second differential voltages for generating a positive temperature coefficient voltage.

2. An integrated circuit voltage and temperature compensated circuit as recited in claim 1 wherein:

a. the value of said first differential voltage is substantially independent of the magnitude of the current in said first current path: and

b. the value of said second differential voltage is substantially independent of the magnitude of the current in said second current path.

3. An integrated circuit voltage and temperature compensated circuit as recited in claim 2 wherein:

a. said first differential voltage has a magnitude represented by the number M, where M is any positive number representing a ratio of junction related areas of said at least two serially interconnected PN junctions of said first current path; and

b. said second differential voltage has a magnitude represented by the number N where N is any positive number representing another ratio of junction related areas of said at least two serially interconnected PN junctions of said second current path.

4. An integrated circuit voltage and temperature compensated circuit as recited in claim 3 wherein:

a. the positive temperature coefficient voltage developed across said reference impedance has a magnitude represented by the product M X N. where M is any positive number representing a ratio of junction related areas of said serially interconnected PN junctions of said first current path, and where N is any positive number representing another ratio of junction related areas of said at least two serially interconnected PN junctions of said second current path.

5. An integrated circuit voltage and temperature compensated circuit as recited in claim 4 wherein:

a. said first circuit path includes first and second interconnected bipolar transistors and wherein said at least two serially interconnected PN junctions are constituted by the base-to-emitter junctions of said first and second interconnected transistors;

b. said second current path includes third and fourth interconnected bipolar transistors and wherein said at least two serially interconnected PN junctions are constituted by the base-to-emitter junctions of said third and fourth interconnected transistors.

6. An integrated circuit voltage and temperature compensated circuit as recited in claim 5 wherein:

a. said second and fourth transistors comprise multiemitter transistors, the ratio of the emitter area of said second transistor to the emitter area of said first transistor being represented by M. the ratio of the emitter area of said fourth transistor with respect to the emitter area of said third transistor being represented by N.

7. An integrated circuit voltage and temperature compensated circuit as recited in claim 3 further comprising:

a. semiconductor means coupled to said voltage source for generating a negative temperature coefficient voltage;

b. said semiconductor means being coupled to said reference impedance means for producing a voltage and temperature compensated circuit. 

1. An integrated circuIt voltage and temperature compensated circuit comprising: a. a reference impedance coupled to a voltage source, said voltage source generating a first and second current; b. a first path coupled to said impedance means for receiving said first current; c. a second path coupled to said reference impedance for receiving said second current; d. said first current path including at least two serially interconnected PN junctions for generating a first differential voltage; e. said second current path including at least two serially interconnected PN junctions for generating a second differential voltage; and f. said reference impedance means being responsive to said first and second differential voltages for generating a positive temperature coefficient voltage.
 2. An integrated circuit voltage and temperature compensated circuit as recited in claim 1 wherein: a. the value of said first differential voltage is substantially independent of the magnitude of the current in said first current path; and b. the value of said second differential voltage is substantially independent of the magnitude of the current in said second current path.
 3. An integrated circuit voltage and temperature compensated circuit as recited in claim 2 wherein: a. said first differential voltage has a magnitude represented by the number M, where M is any positive number representing a ratio of junction related areas of said at least two serially interconnected PN junctions of said first current path; and b. said second differential voltage has a magnitude represented by the number N where N is any positive number representing another ratio of junction related areas of said at least two serially interconnected PN junctions of said second current path.
 4. An integrated circuit voltage and temperature compensated circuit as recited in claim 3 wherein: a. the positive temperature coefficient voltage developed across said reference impedance has a magnitude represented by the product M X N, where M is any positive number representing a ratio of junction related areas of said serially interconnected PN junctions of said first current path, and where N is any positive number representing another ratio of junction related areas of said at least two serially interconnected PN junctions of said second current path.
 5. An integrated circuit voltage and temperature compensated circuit as recited in claim 4 wherein: a. said first circuit path includes first and second interconnected bipolar transistors and wherein said at least two serially interconnected PN junctions are constituted by the base-to-emitter junctions of said first and second interconnected transistors; b. said second current path includes third and fourth interconnected bipolar transistors and wherein said at least two serially interconnected PN junctions are constituted by the base-to-emitter junctions of said third and fourth interconnected transistors.
 6. An integrated circuit voltage and temperature compensated circuit as recited in claim 5 wherein: a. said second and fourth transistors comprise multi-emitter transistors, the ratio of the emitter area of said second transistor to the emitter area of said first transistor being represented by M, the ratio of the emitter area of said fourth transistor with respect to the emitter area of said third transistor being represented by N.
 7. An integrated circuit voltage and temperature compensated circuit as recited in claim 3 further comprising: a. semiconductor means coupled to said voltage source for generating a negative temperature coefficient voltage; b. said semiconductor means being coupled to said reference impedance means for producing a voltage and temperature compensated circuit. 